In recent years, with becoming smaller and denser of semiconductor packages, a ball grid array (BGA) type semiconductor package that is flip chip bonded and wire bonded in which a bare chip is directly mounted facedown on a substrate has been developed.
Further, with emergence of a camera-integrated VTR, a cellular telephone and the like, a portable equipment having a small package which has substantially the same size as that of the bare chip, so-called CSP. (chip size/scale package) has appeared. The development of the CSP has been rapidly pursued and the demands of the market have been increased.
Technique of a conventional wiring substrate using a flexible film for TAB is disclosed in Japanese Patent Application Publication No. 7-66932. According to this technique, as shown in FIG. 1 of this publication, in an electrical connection and short circuit frame in an etching wiring 4 for an integrated circuit, a lead wire 1 extending to a connecting point 2 with respect to a wire of adjacent integrated circuits is formed in a meandering manner. Therefore, by cutting between adjacent integrated circuits at a cutting position 7, the integrated circuits can be divided without wasting material. As a result, all the short circuit connections of the meandering pattern are separated by cutting at the cutting position 7, and the meandering pattern is formed as a terminal (lead wire) in the integrated circuit.
FIG. 10 is a partial plan view of adjacent chip circuits showing one pattern of another conventional common electrode line for plating described in Japanese Patent Application Laid-open No. 9-55398.
In FIG. 10, in a semiconductor substrates 10, a plurality of chip circuits are collectively formed on a same semiconductor substrate 10. The semiconductor substrate 10 comprises a silicon substrate, and is cut into a predetermined size to divide into a large number of chip circuits.
Common electrode lines for plating 12 are connected to electrode pads 14 of said each adjacent chip circuit 10A. The common electrode lines for plating 12 are meandering in a crank shape across cut lines X and Y.
Wiring (conductive) patterns 13 of each chip circuit 10A are formed of the common electrode lines for plating 12.
The electrode pads 14 are disposed on an active surface side of the semiconductor substrate 10. Each electrode pad 14 is connected to the corresponding wiring pattern 13 and functions as an external connecting electrode.
Each common electrode line for plating 12 has a predetermined width, and meanders in the crank shape across the cut line X. Since the common electrode lines for plating 12 are formed on the same surface of the main substrate 10, a constant gap G1 is provided between the wiring patterns 13 so that the adjacent common electrode lines for plating 12 do not come into contact with each other.
FIG. 11 is an enlarged plan view of an essential portion showing a pattern of another conventional common electrode line for plating. The common electrode lines for plating 12 comprise a main line 12a sequentially formed between wiring patterns (conductive patterns), and branch lines 12b branched from the main line 12a for connecting particular pads (only a portion is shown in FIG. 11). In this case also, a constant gap G2 is provided between the wiring patterns 13 so that adjacent common electrode lines for plating 12 (12a, 12b) do not come into contact with each other.
In these conventional techniques, the common electrode lines for plating 12 for short-circuiting pad patterns are provided before the electrolytic plating processing and then, electrode material is deposited on each pad pattern by the electrolytic plating processing to form a plurality of pad electrodes collectively. At the time of the electrolytic plating processing, all the pad patterns have the same electric potential by the common electrode lines for plating 12, and a deposition amount and a film thickness of the electrode material of each pad pattern are prevented from being varied. By forming the common electrode lines for plating 12 across the cut lines X and Y in a meandering manner, even if slight positional deviation of dicing is generated in a dicing step, it is possible to reliably (shut off conductively) cut the common electrode lines for plating 12, and short caused by short circuit of the common electrode lines for plating in each chip circuit 10A is eliminated. Further, since the cutting width in the dicing step is narrow, the chip circuit 10A can be cut and divided without waste of the substrate material.
However, the above-described conventional common electrode lines for plating have the following problems.
That is, the common electrode lines for plating 12 are formed such as to meander in the crank shape across the cut line. Each common electrode line for plating 12 has a predetermined width and is formed on the same surface of the main substrate. Therefore, it is necessary to provide predetermined gaps G1 and G2 between the wiring patterns 13 and 13 so that the adjacent common electrode lines for plating, or the common electrode line for plating and the wiring pattern (conductive pattern) do not come into contact with each other. Thus, the number of terminals (the number of pins) formed per one side of the circuit substrate is limited, and it is difficult to form the terminals at high density.
Even if the shape of the common electrode lines for plating is changed from the crank shape into an inclined shape, it is difficult to increase the number of terminals by the same reason.
Thereupon, it is an object of the present invention to provide high reliable common electrode lines for plating of a main substrate in which the waste of substrate material at the time of dicing is eliminated, the gap between the wiring patterns is narrowed as small as possible, the number of terminals per one side of each circuit substrate is increased, and the terminals can be formed at high density.